Two-dimensional (2D) discrete cosine transformation (DCT) operations are commonly used in Motion Picture Experts Group (MPEG) video encoding to decorrelate the image samples which allows compression of the input data. DCT is a close approximation of the optimal Karhunen-Loeve transform for a wide class of images. In the IDCT engine, an inverse discrete cosine transformation (IDCT) is used to recorrelate the image samples. In MPEG encoding or decoding, a 2D 8×8 IDCT is normally used.
Since IDCT is an orthogonal transformation, the 2D transform can be computed by first performing one-dimensional (1D) transformations on the eight rows and then performing 1D transformations on the columns of the result from the row stage. Those skilled in the art usually refer to this process as “row-column decomposition.” Various fast algorithms have been developed for computing the 1D IDCT, but are outside the scope of the present discussion.
To perform MPEG decoding, a software implementation of the IDCT has been developed for the ZSP500 Digital Signal Processor (see, ZSP500 Digital Signal Processor Technical Reference Manual, LSI Logic Corp., Milpitas, Calif., USA, 2003, incorporated herein by reference in its entirety). To take advantage of the architectural features of the ZSP500 processor, an Even-Odd decomposition IDCT algorithm (see, e.g., Hung, et al., “A Compact IDCT design for MPEG Video Decoding,” in Proceedings 1997 IEEE Workshop on Signal Processing Systems (SiPS 1997), November 1997) incorporated herein by reference in its entirety. This algorithm has uniform butterfly structure that makes it amenable for implementing on processors such as ZSP500. Unfortunately, software implementations are computationally burdensome, reducing the speed at which a DSP can perform IDCT and reducing processor bandwidth perhaps useful for purposes.
Accordingly, what is needed in the art is a hardware-based IDCT circuit. More specifically, what is needed in the art is a hardware-based IDCT circuit that is fast and efficient and can be used as a co-processor for a DSP, for example.